The present invention relates to a semiconductor device, and more particularly, to an internal voltage generating circuit for generating an internal voltage that is maintained at a stable voltage level, regardless of a frequency variation of an external clock.
Most semiconductor devices, e.g., dynamic random access memory (DRAM), include an internal voltage generating circuit inside a chip to generate internal voltages necessary for operations of internal circuits. The internal voltage generating circuit generates internal voltages of various levels by using an external power supply voltage (VDD) and a ground voltage (VSS).
The generation of the internal voltages includes an operation of generating a reference voltage and an operation of charge-pumping or down-converting the generated reference voltage.
Examples of a representative internal voltage generated using the charge pumping operation include a high voltage (VPP) and a back bias voltage (VBB), and examples of a representative internal voltage generated using the down-converting operation include a core voltage (VCORE).
The high voltage (VPP) is a voltage higher than an external power supply voltage (VDD). Upon access to a memory cell, the high voltage (VPP) is applied to a word line connected to a gate of a cell transistor in order to compensate loss of cell data, which is caused by a ID threshold voltage (Vth) of the cell transistor.
The back bias voltage (VBB) is a voltage lower than an external ground voltage (VSS). The back bias voltage (VBB) reduces the variation of the threshold voltage (Vth) of the cell transistor, which is caused by a body effect, thereby improving the operation stability of the cell transistor and reducing a channel leakage current generated at the cell transistor.
The core voltage (VCORE) is a voltage lower than an external power supply voltage (VDD) and higher than a ground voltage (VSS). The core voltage (VCORE) reduces power that is necessary to maintain a voltage level of data stored in a memory cell, and is used for stable operation of the cell transistor.
The internal voltage generating circuit generating the internal voltages (VPP, VBB and VCORE) is designed to operate with a predetermined deviation value within an operating voltage region and an operating temperature range of the semiconductor memory device.
FIG. 1 is a block diagram of a conventional internal voltage generating circuit.
Referring to FIG. 1, the conventional internal voltage generating circuit for generating an internal voltage VINT includes a bandgap reference voltage generator 140, an internal voltage detector 100, and an internal voltage driver 120. The bandgap reference voltage generator 140 generates a reference voltage VREF_INT that is constantly maintained at a target level, regardless of variation of process, voltage and temperature (PVT) of the semiconductor device. The internal voltage detector 100 detects a level of an internal voltage (VINT) terminal, based on the target level of the reference voltage VREF_INT, to generate an internal voltage detection signal VINT_DET. The internal voltage driver 120 pulls up the internal voltage terminal in response to the internal voltage detection signal VINT_DET.
The internal voltage VINT generated through the above-described processes is input to an internal circuit 160 and enables the internal circuit 160 to perform its internal operation.
Specifically, the internal voltage detector 100 activates the internal voltage detection signal VINT_DET when the level of the internal voltage terminal is lower than the reference voltage VREF_INT that is constantly maintained at the target level, regardless of PVT variation. On the other hand, the internal voltage detector 100 deactivates the internal voltage detection signal VINT_DET when the level of the internal voltage terminal is higher than the reference voltage VREF_INT.
The internal voltage driver 120 pulls up the internal voltage terminal with a predefined drivability when the internal voltage detection signal VINT_DET is in the activated state.
In summary, the internal voltage detector 100 and the internal voltage driver 120 detect the phenomenon that the level of the internal voltage terminal is lowered due to the operation of the internal circuit 160, and make the internal voltage terminal have the target level of the reference voltage VREF_INT.
With respect to the internal voltage terminal, the internal circuit 160 is a current load that is variously variable. That is, the internal circuit 160 may vary the level of the internal voltage VINT when its internal operation is performed according to the operation mode of the semiconductor device.
For example, the internal circuit 160 uses a large amount of the internal voltage VINT in the read/write operation, that is, when the data input/output operations are performed. Thus, reduction in the level of the internal voltage terminal is relatively large. On the other hand, the internal circuit 160 hardly uses the internal voltage VINT in the power-down mode where the data input/output operations are not performed. Thus, reduction in the level of the internal voltage VINT is relatively small.
Therefore, the level of the internal voltage terminal repetitively rises and falls above and below the target level of the reference voltage VREF_INT according to the operations of the internal voltage detector 100, the internal voltage driver 120, and the internal circuit 160.
When the level variation width of the internal voltage terminal, centering on the level of the reference voltage VREF_INT, does not exceed the predefined level width, the operation of the semiconductor device may not be greatly affected.
However, when the level variation width of the internal voltage terminal, centering on the level of the reference voltage VREF_INT, exceeds the predefined level width, the operation of the semiconductor device may not operate normally.
To solve this problem, the level variation width of the internal voltage terminal should be controlled such that it falls within the predefined level width.
To this end, the operating speed of the internal voltage detector 100 has been increased relatively faster. That is, the internal voltage detector 100 detects the level of the internal voltage terminal more frequently during the same time. In this way, the level variation width of the reference voltage terminal, centering on the level of the reference voltage VREF_INT, can fall within the predefined level width.
For example, if the internal voltage detector 100 detects the level variation of the internal voltage terminal relatively frequently, it can detect the level of the level of the internal voltage terminal relatively fast even when it rapidly falls, and operate the internal voltage driver 120. It can prevent the level of the internal voltage terminal from further falling at the moment when the internal voltage driver 120 starts to operate, and it increases the level of the internal voltage terminal. Therefore, it is possible to reduce the level failing width of the internal voltage terminal, centering on the level of the reference voltage VREF_INT.
Likewise, if the internal voltage detector 100 detects the level variation of the internal voltage INT terminal relatively frequently, the rapid rise of the level of the internal voltage terminal due to the operation of the internal voltage driver 120 can be detected relatively fast. Therefore, the operation of the internal voltage driver 120 can be stopped. At the moment when the operation of the internal voltage driver 120 is stopped, the level of the internal voltage terminal does not further rise and immediately falls. Consequently, the level rise width of the internal voltage terminal, centering on the reference voltage VREF_INT, can be reduced.
However, a predetermined amount of current is consumed whenever the internal voltage detector 100 detects the level of the internal voltage terminal. Thus, an amount of current relatively increases when the internal voltage detector 100 detects the level of the internal voltage terminal relatively frequently. If the operating speed of the internal voltage detector 100 increases, an amount of current consumed in the semiconductor device will considerably increase.
In addition, despite the fact that the case where the level of the internal voltage terminal slowly changes occurs more often than the case where the level of the internal voltage terminal rapidly changes, it is unreasonable to increase the operating speed of the internal voltage detector 100 in order for preparing for the case where the level of the internal voltage terminal rapidly changes.
This means that increasing the operating speed of the internal voltage detector 100 is allowed to some extent. Increasing the operating speed of the internal voltage detector 100 in order to prevent the rapid level variation of the internal voltage terminal has the tradeoff relationship with increase in an amount of current consumed in the internal voltage detector 100. To solve the two problems at a time, the designer must find the level variation width of the internal voltage terminal having a relatively low error probability through various test operations, and design the semiconductor device such that it performs the operation of properly maintaining the operating speed of the internal voltage detector 100 so that the semiconductor device can operate normally without greatly increasing the current consumption.
Meanwhile, the level of the power supply voltage VDD supplied to the semiconductor device is gradually lowered and the operating speed of the semiconductor device is gradually increasing.
The fast operating speed of the semiconductor device means that the frequency of the external clock applied to the semiconductor device is high. That is, as the frequency of the external clock is increasing, the semiconductor device can operate at higher speed.
Also, the high-speed operation of the semiconductor device as the frequency of the external clock increases means that the internal circuit 160 of the semiconductor device will use the internal voltage VINT much more. That is, it means that the level of the internal voltage terminal may change more rapidly.
Due to the increased frequency of the external clock, the level of the internal voltage terminal changes more rapidly. Even though the internal voltage detector 100 and the internal voltage driver 120 operate at the typical speed, it is impossible to prevent the phenomenon that the level of the internal voltage terminal rises and falls centering on the level of the internal voltage terminal.
That is, it is impossible to prevent the increase in the level variation width of the internal voltage terminal, which is caused by the increased frequency of the external clock, at the operating speed of the internal voltage detector 100 where its error probability is low and its current consumption is not greatly increased. Therefore, the semiconductor device cannot operate normally, increasing the error probability.
Increasing the operating speed of the internal voltage detector 100 without any preparation will cause the above-described problem that an amount of current consumed in the semiconductor device is increased too much.
Therefore, whenever the operating speed of the semiconductor device changes, that is, when the frequency of the external clock applied to the semiconductor device changes, the designer must again find the level variation width of the internal voltage terminal having a relatively low error probability through test operations, and design the semiconductor device such that it performs the operation of properly maintaining the operating speed of the internal voltage detector 100 so that the semiconductor device can operate normally without greatly increasing the current consumption.